1. Field of the Invention
The present invention relates to a field effect transistor and a method of manufacturing a field effect transistor.
2. Related Art
Following an improvement in performance, microfabrication and an increase of a density of a metal-oxide-semiconductor (MOS) field effect transistor (FET) are repeatedly achieved, and the MOS FET is increasingly reduced in size. A film thickness of a gate insulating film, for example, which consists of SiO2, and a transistor operation of which can be checked, has reached less than one nanometer in a study phase. The thickness corresponds to that of six atomic layers of SiO2. However, the reduction in size of the FET following a reduction in thickness of the gate insulating film disadvantageously causes an increase of a leak current, and an increase of power consumption. For this reason, a technique for suppressing the increase of the leak current while realizing the reduction in size is desired.
As a method for suppressing the increase of the leak current while reducing the size of the transistor, there is proposed a method using a material having a higher dielectric constant (a higher dielectric constant film) such as an Hf oxide in place of the conventional SiO2 film or SiON film. The use of the high dielectric constant film has an advantage in that the leak current can be reduced while making a film thickness equivalent to the thickness of the SiO2 film (hereinafter “EOT” (Equivalent Oxide Thickness)) thinner. The use of the high dielectric constant film has, however, disadvantages in that a carrier mobility is deteriorated and a driving force is thereby deteriorated as compared with the use of the SiO2 film due to an increase of the density of an interface state and impurity scattering in the high dielectric constant film. Development of a technique for preventing deterioration of the carrier mobility is, therefore, desired.
Furthermore, there is no avoiding confronting a physical limit to the improvement in performance by the microfabrication. A technique for improving the MOSFET without relying on the microfabrication is also required. Examples of the technique include new structured MOSFET's for which new concepts such as band engineering and three-dimensional structure are introduced. Specifically, a very thin film SOI (Silicon on Insulator) MOSFET, a Fin MOSFET, a strained Si-MOSFET, and the like are potential new structured MOSFET's.
The very thin SOI MOSFET is characterized by burying an SiO2 film in a substrate to thereby make a channel region thin. Since complete depletion can be realized at a low impurity concentration, a short-channel effect can be suppressed and a switching rate can be accelerated. However, Si in the channel region is applied with a compressive strain from the buried SiO2 film, an electron mobility is disadvantageously deteriorated. In addition, in order to apply a substrate potential, complex and elaborate manufacturing steps of etching the SiO2 film, and then epitaxially growing the Si are disadvantageously required, and a manufacturing cost is thereby, disadvantageously increased. The Fin MOSFET is a development type of the very thin SOI MOSFET and characterized by including a Fin channel region formed on a buried SiO2 film. Since the Fin MOSFET is double-gate MOSFET having right and left sides surrounded by gate electrodes, respectively, it is expected to not only suppress the short-channel effect but also increase an ON current, as compared with a conventional single-gate MOSFET.
However, similarly to the very thin SOI MOSFET, the conventional Fin MOSFET is structured so that the channel receives a compressive strain from the buried SiO2 film. Due to this, the conventional Fin MOSFET is said to have a disadvantage of deterioration of an electron mobility. In addition, similarly to the very thin SIO MOSFET, complex and elaborate manufacturing steps are required so as to apply a substrate potential (see, for example, Japanese Patent Application Laid-Open No. 2002-118255). Further, since the right and left sides of the Fin MOSFET are surrounded by the gate electrodes, boron spike from the gate electrodes conspicuously occurs, thereby disadvantageously making it difficult to control a threshold.
The strained Si-MOSFET using SiGe is characterized by forming a substrate that includes an SiGe layer (to be also referred to as “SGOI (SiGe on Insulator) substrate”, hereinafter) on an insulating film, and by epitaxially growing Si on the SGOI substrate. Since Si in a channel region is applied with a tensile strain from the SiGe layer, a carrier mobility can be advantageously improved. It is confirmed that the n-MOSFET has about 80% improvement and that the p-MOSFET has about 20% improvement in carrier mobility. The reason that the p-MOSFET does not exhibit notable improvement in mobility is not clear quantitatively. However, it is said that this is partly because only the tensile strain is applied to an Si layer serving as the channel region when the Si layer is formed on the SiGe layer. If the compressive strain is applied to the channel region, the mobility may possibly be improved. Therefore, a compressively strained p-MOSFET having an SiGe layer formed as a channel region is studied. According to a study report, the p-MOSFET has 130% improvement in hole mobility. Therefore, it is highly likely that a driving force of the p-MOSFET is improved by forming the channel region consisting of Si applied with a higher compressive strain. However, in the manufacturing of the SiGe substrate (or SGOI) substrate, complex methods including an SIMOX method, a bonding method, and an oxidation-concentration method are used, thereby disadvantageously increasing a manufacturing cost. Development of a technique for easily applying the tensile strain or the compressive strain in a manufacturing process is desired. Further, if the channel region is thinner, Ge diffused from the SiGe substrate and pass-through dislocation accelerate carrier scattering. Therefore, a method for manufacturing a strained Si without using SiGe is desired.
As stated above, there is no avoiding confronting the limit to the improvement in performance by the microfabrication. It is, therefore, necessary to propose a new MOSFET structure without relying on the microfabrication.
Nevertheless, the potential new structured MOSFET's such as the very thin SOI-MOSFET, the Fin MOSFET, and the strained SI-MOSFET have the disadvantages, as described. The very thin SOI-MOSFET and the Fin MOSFET have the disadvantage of the deterioration of the electron mobility because Si in the channel region is applied with the compressive strain from the buried SiO2 film. The strained Si-MOSFET has the following disadvantage. If the channel region is thinner, then the carrier scattering is accelerated by Ge diffused in the channel region, and the mobility is deteriorated.